Recently, a large number of delay lines is used for timing adjustment and the like in a semiconductor device. For example, a double data rate (DDR) is known as a standard for connecting a central processing unit (controller) and an external memory (DIMM), and standards such as a DDR2, a DDR3, and a DDR4 have been developed in keeping with a higher speed of data transfer.
In the DDR standard, strict timing specifications have been defined for various electrical signals exchanged with a memory when reading data from a memory and writing data to a memory. In addition, a variance within a certain range is assumed in a timing in which a signal is received from the memory. In a semiconductor device that operates in accordance with the DDR standard, a large number of delay lines are used in a memory controller in order to finely adjust a timing of an electrical signal.
In the delay line, a large number of buffer circuits (delay elements), each of which causing a minute delay, are provided so as to be connected in series, such that a desired delay amount is obtained by adjusting the number of buffer circuits connected (passed through). A delay amount of one delay element corresponds to a resolving power to set delay for a delay line. In order to set a delay amount with a high degree of accuracy, a delay amount for each of the delay elements is set to a small value. To obtain a large maximum delay amount, the number of connected delay elements is increased. Thus, a high accuracy delay line with a large maximum delay amount involves a complex circuit and an increased circuit scale.
The delay line is a circuit that outputs an input signal after delaying the signal for a certain amount of time. The delay line is thus a buffer (or inverter) logically. In an inspection for shipping, etc., not only a logical test of the delay line, but also a reasonableness test of a delay (accuracy of a delay amount per stage of a delay element) is called for.
A method using a scan circuit is known as a method for measuring a delay amount. However, a delay amount and setting resolution desired for a delay line are very small values compared to a clock cycle of a circuit, making it difficult to measure a delay in a delay line accurately.
For the reasons described above, there is an issue of a failure being difficult to detect if bits adjacent to each other in a delay line delay setting signal are short-circuited. This is because it is difficult to detect a difference between delay setting signals next to each other, as the difference of the amount of delay to be set is still small. There are other types of failures in a delay line, and it is desirable that a delay is accurately measured in each case.
The followings are reference documents.
[Document 1] Japanese Laid-open Patent Publication No. 2000-285144,
[Document 2] Japanese Laid-open Patent Publication No. 2013-152249, and
[Document 3] Japanese Laid-open Patent Publication No. 2003-60489.